1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a structure allowing high speed testing of a semiconductor memory device. More particularly, the present invention relates to a structure for selecting, at high speed, a word line in a semiconductor memory device at the time of a test operation.
2. Description of the Background Art
Referring to FIG. 8, a conventional semiconductor memory device 200 includes a control circuit 31, an address buffer 34, a memory cell array 7, a row decoder 12 and a column decoder 13.
Memory cell array 7 includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells.
Control circuit 31 receives external control signals /RAS (external row address strobe signal), /CAS (external column address strobe signal), /WE (write enable signal), /OE (external output enable signal) and so on, and generates various internal control signals.
Address buffer 34 receives an internal control signal from control circuit 31 through a control signal bus a3. Address buffer 34 takes in external address signals A0 to Ai applied through an address terminal 8 and outputs an internal row address signal and an internal column address signal-to an internal address bus a4, in response to the applied internal control signal.
Row decoder 12 receives an internal row address strobe signal, which is an internal control signal, from control circuit 31 through control signal bus a3. Row decoder 12 is activated in response to the internal row address strobe signal, and it decodes the internal row address signal output from address buffer 34 and selects a word line of memory cell array 7.
Column decoder 13 receives an internal column address strobe signal from control circuit 31 through control signal bus a2. Column decoder 13 is activated in response to the internal column address strobe signal, and it decodes the internal column address signal output from address buffer 34 and selects a bit line of memory cell array 7.
Semiconductor memory device 200 further includes a sense amplifier, an I/O gate, an input buffer 15 and an output buffer 16. In FIG. 8, the sense amplifier and the I/O gate are generally represented by one block 14.
The sense amplifier receives an internal control signal from control circuit 31 through control signal bus a3. Based on the applied internal control signal, the sense amplifier detects and amplifies data of a memory cell connected to the selected word line of memory cell array 7.
I/O gate connects the selected bit line of memory array 7 to an internal data bus a1 in response to a column selection signal output from column decoder 13.
Input buffer 15 receives an internal control signal from control circuit 31 through a control signal bus a2. Based on the applied internal control signal, input buffer 15 receives external write data DQ0 to DQj applied to data input/output terminal 17, generates an internal write data and transmits the generated internal write data to internal data bus a1.
Output buffer 16 receives an internal control signal from control circuit 31 through control signal bus a2. Based on the applied control signal, output buffer 16 generates, from the internal read data read to internal data bus a1, external read data DQ0 to DQj and outputs the data to data input/output terminal 17.
Internal structure of the memory cell array will be briefly described with reference to FIG. 9. FIG. 9 shows, as a representative, word lines WL0, WL(I-1), WL1, WL(I+1) and a pair of bit lines BL and /BL.
A memory cell M is arranged at a crossing portion between a pair of bit lines and a word line. FIG. 9 shows, as representative, a memory cell M1 arranged at a crossing portion of word line WL(I-1) and bit line /BL, a memory cell M2 arranged at a crossing portion of word line WL1 and bit line BL, and a memory cell M3 arranged at a crossing portion of word line WL(I+1) and bit line /BL.
Each of memory cells M1 to M3 includes a capacitor 50 and an access transistor 51. Capacitor 50 stores information in the form of charges. Access transistor 51 is rendered conductive in response to a potential of a corresponding word line, and connects the corresponding bit line to capacitor 50. Access transistor 51 consists of an N channel MOS transistor.
To a word line selected corresponding to the internal row address signal, a row selection signal is transmitted from row decoder 12. Sense amplifiers included in block 14 are arranged corresponding to respective bit line pairs BL and /BL, and differentially amplify potential of the corresponding bit line pair.
In a reading operation, as the potential of the selected word line increases, potential of a word line which is not selected may possibly float, causing leakage of charges from a capacitor of a memory cell belonging to the non-selected word line to a corresponding bit line.
Generally, capacitor value of a memory cell capacitor is set such that electrode potential of the capacitor would not be significantly decreased even when there is leakage of charges.
However, because of variation in manufacturing, there may be a so-called defective memory cell of which capacitor value is small. In such a defective memory cell, electrode potential of the capacitor is considerably decreased by a minor leakage of charges. This results in inversion of stored data.
Existence of such a defective memory cell is fatal to the operation of the semiconductor memory device.
To cope with this problem, a test for detecting a defective memory cell which causes change in stored data, called disturb test, has been known.
In the disturb test, word lines other than the word line connected to a memory cell of interest are selected for a prescribed number of times (disturb number), and whether the data of the memory cell of interest is retained properly or not (whether the memory cell is defective or not) is determined.
The disturb test in a conventional semiconductor memory device will be described with reference to FIG. 10.
Referring to FIG. 10, at the time of a disturb test, a plurality of semiconductor memory devices DR (in the figure, represented by DR11, . . . , DRmn) are placed on a test board 91. Semiconductor memory device DR is connected to a signal line SG. The signal line SG is connected to a test apparatus 90.
In the disturb test, first, data at an H (logic high) level or an L (logic low) level data is written to semiconductor memory device DR. Thereafter, a clock signal and an external address signal required for selecting a specific word line are applied from test apparatus 90 to signal line SG. In response to the clock signal (more specifically, external control signal /RAS) and the address signal received from signal line SG, semiconductor memory device DR selects a word line.
After repeating the operation of selecting a specific word line for a prescribed number of times, it is determined by test apparatus 90 whether the data of the memory cell of interest is retained properly.
Since the test is performed on the semiconductor memory device in accordance with the procedure described above, the time required for the test depends on the clock signal output from test apparatus 90. Therefore, when the minimum clock length of the signal output from test apparatus 90 is very long, the time required for the test would be very long, especially because the number of test operation is large in the disturb test. Further, only the disturb test of long period is possible by such test apparatus 90. Therefore, correlation with test results obtained by a test apparatus having short minimum clock length cannot be obtained.
A solution is proposed Japanese Patent Laying-Open No. 8-227598 "Semiconductor Storage Device and Its Word Line Selecting Method" in which an address signal for selecting a word line is generated internally. However, according to this proposal, an internally provided address counter selects a word line. Therefore, it is not possible to know from the outside what word line is selected.